The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/11/2022 |
2.4 |
• Added Y_U_V10 . • Updated Table: Vivado IDE Parameter to User Parameter Relationship . • Updated the Upgrading in the Vivado Design Suite section. |
|
10/27/2021 |
2.3 |
• Added support for 16K resolution and 3 Planar video format • Updated enhancement for field ID signal |
|
08/09/2021 |
2.2 |
• Added support for Versal® example design in Table: Supported Platforms . |
|
02/04/2021 |
2.2 |
• Updated Vitis Software Platform workflow for v2.2. |
|
07/08/2020 |
2.1 |
• Updated AXI-Stream Video Interface section in Chapter 2. • Updated Control (0x0000) Register in Chapter 2. • Updated Stride (0x0020) Register in Chapter 2. • Updated Plane1 Buffer (0x0030) and Plane 2 Buffer (0x003C) Registers in Chapter 2. • Updated Samples Per Clock description in Chapter 4. |
|
12/19/2019 |
2.1 |
• Vitis flow updated in Chapter 5. |
|
11/14/2018 |
2.1 |
• Added support for 8K30 in Features . • Updated UG934 link in fid error . • Added Table: IP Format to Common Video Pixel Format . • Updated UG934 link in Note in Table: IP Format to Common Video Pixel Format . • Fixed AR 68764 link. |
|
04/04/2018 |
2.0 |
• Added support for interlaced video • Added BGR8 video format • Added support for ZCU102, ZCU104, and ZCU106 boards in the example design. |
|
10/04/2017 |
2.0 |
Added new video formats, added second buffer for semi-planar formats, added support for 64-bit addressing on memory interfaces. |
|
04/05/2017 |
1.0 |
Initial Xilinx release. |