The IP’s Buffer parameters can be changed dynamically and the change is picked up immediately. If the Width , Height , Stride , or Video Format must be changed or the entire system restarted, it is recommended that pipelined Xilinx® IP video cores are disabled/reset from system output towards the system input, and programmed/enabled from system output to system input.
Pending AXI transactions can be flushed before reseting the IP. Assert and hold Bit[5] of the Control register. Bit[6] asserts when the flush is complete and then the IP can be reset.
For interlaced video, with the ap_ready interrupt, the current Field ID can be read for the Video Frame Buffer Write IP, and the next Field ID can be programmed for the Frame Buffer Read IP.