The Video Frame Buffer Read and Video Frame Buffer Write cores use industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the cores. This Figure illustrates the Video Frame Buffer Read diagram. Each IP has three AXI interfaces:
• AXI-Lite control interface ( s_axi_CTRL )
• AXI4-Stream streaming video output ( m_axis_video ) or input ( s_axis_video )
• Memory mapped AXI4 interface ( m_axi_mm_video )
This Figure illustrates the Video Frame Buffer Write diagrams.
