The Video Frame Buffer Read and Video Frame Buffer Write cores are delivered with a bare-metal driver as part of the Vitis installation. The driver follows a layered architecture wherein layer 1 provides basic register peek/poke capabilities and requires users to be familiar with the register map and inner workings of the core. Layer 2, on the other hand, abstracts away all the lower level details and provides an easy-to-use functional interface to the Video Frame Buffer Read and Video Frame Buffer Write cores. Xilinx ® recommends always using layer 2 APIs to interact with the core.