- Read core_config register to ensure that the control ready bit is set to '1' before enabling the core at any time (for example, after reset or after disabling the core).
- Select the required settings for Video Mode, EoTp, and so on. in the Protocol configuration register.
- Based on peripheral resolution and timing requirements, arrive the word count values for all the different packets to be sent in the video frame (HBP, HFP, HSA, HACT, etc.).
- Enable the core and send a video stream on the input interface.
- The core starts adding the required markers and then consumes the input video stream when the internal timing reaches the active portion of the video.
- All along this sequence, either continuously poll or wait for external interrupt (if enabled) and read the Interrupt status register for any errors/status reported.
Figure 1. Core Programming Sequence - 1
