|
Core Specifics |
| Supported Device Family
1
|
UltraScale+™
HBM |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream, and AXI3-Full Interfaces. |
| Resources |
See Performance. |
| Provided with Core
|
| Design Files |
Encrypted Verilog RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraint (XDC) |
| Simulation Model |
Verilog source code |
| Supported S/W Driver
2
|
Vits Networking P4 |
| Tested Design Flows
3
|
| Design Entry |
Vitis™
Networking P4 |
| Simulation
4
|
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Xilinx
Vivado Synthesis |
| Support |
| Provided by Xilinx® at the Xilinx
Support web page
|
- For a complete list of supported devices, see
the
Vivado®
IP catalog.
- Standalone driver details can be found online.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
- Modelsim, Questa, VCS, Xcelium, and Xsim are
supported. Refer to
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973) for information on
version compatibility.
|