System Interface Ports - 2.2 English

System Interface Ports - 2.2 English - PG319

Semi-Ternary CAM Search LogiCORE IP Product Guide (PG319)

Document ID

PG319

Release Date

2021-07-27

Version

2.2 English

Table 1. System Interface
Port Name	I/O	Clock	Description
rstn	I		Asynchronous reset (active_low). The reset input is synchronized internally to both the ram_clk and key_clk domains.
rst_busy	O	s_axi_aclk	Reset Busy is an active high indicator that the core is currently in reset state.
ram_clk	I		The ram clock is used for the internal RAM and match logic.
sbiterr	O	key_clk	Single-bit error output status. A single-bit error has been detected and corrected by the ECC scrubbing mechanism.
dbiterr	O	key_clk	Double-bit error output status. A double-bit error has been detected by the ECC scrubbing mechanism.
debug_status[31:0]	O		Debug status port.