Transmit Fixed Ethernet Startup Procedure when Reconfiguring (not using tx_core_reset) - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
Release Date
2.1 English

The DCMAC FixedE path employs an internal time-sliced MAC that is a channelized core. When adding, removing, or reconfiguring ports, it is usually not appropriate to do a global reset (tx_core_reset). Instead, individual ports can be reset/cleared/flushed independently. Port flushes (and corresponding PHY resets) on reconfigured ports should not affect other active ports that are not being reconfigured.

When following the startup procedure for port reconfiguration, note that stat_tx_local_fault for a particular port will not assert while the PHY is in reset. It is recommended to use stat_tx_local_fault to ensure that the MAC is initialized and the port is clear. The following procedure should be followed:

  • Assert tx_channel_flush and tx_serdes_reset on any active ports that are being reconfigured (or deactivated)
  • Assert tx_channel_flush and tx_serdes_reset on any inactive ports that are being reconfigured to become active
  • Release serdes_reset for active ports
  • Wait for 100 (minimum) core clock cycles
    • or 50 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual)
  • Check/wait for stat_tx_local_fault on active ports
  • Release tx_channel_flush for active ports