Transceiver (SerDes) Interface - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-04-12
Version
2.1 English

The clock and data connections between the DCMAC Subsystem transceiver interface and the GT transceivers varies depending on the selected GT technology and the configured operating mode. This section describes the connectivity between the DCMAC Subsystem and the GT transceivers.

Note: In these tables, <N> = port number 0-5.
Table 1. Transceiver Interface Signal Descriptions: TX Direction
Port Name Clock Domain I/O Description
tx_serdes_data<4*N+0>[79:0] tx_alt_serdes_clk[<N>] O Data to GT
tx_serdes_data<4*N+1>[79:0] tx_alt_serdes_clk[<N>] O Data to GT
tx_serdes_data<4*N+2>[79:0] tx_alt_serdes_clk[<N>] O Data to GT
tx_serdes_data<4*N+3>[79:0] tx_alt_serdes_clk[<N>] O Data to GT
fec_tx_dout_start_<N> tx_alt_serdes_clk[<N>] O Indicates start of codeword.
fec_tx_dout_start_<N>_bh tx_alt_serdes_clk[<N>] O Indicates start of codeword for bottom half of port. Used in 50G FEC-only mode.
tx_serdes_is_am_prefifo_<N> tx_serdes_clk[<N>] O Indicator of alignment marker overhead on the fast-clock side of the output FIFO.
tx_serdes_is_am_<N> tx_alt_serdes_clk[<N>] O Indicates that output SerDes data includes alignment marker overhead. This signal is valid for MAC+PCS mode, and also for PCS, 128GFC, and FlexO modes. It is not valid for FEC-only mode.
Note: When operating in Independent MAC and PCS+FEC mode, the first (following reset) codeword start indication on the TX Flex Interface might not be relayed to the TX Transceiver (Serdes) Interface.
Table 2. Transceiver Interface Signal Descriptions: RX Direction
Port Name Clock Domain I/O Description
rx_serdes_data<4*N+0>[79:0] rx_alt_serdes_clk[<N>] I Data from the GT
rx_serdes_data<4*N+1>[79:0] rx_alt_serdes_clk[<N>] I Data from the GT
rx_serdes_data<4*N+2>[79:0] rx_alt_serdes_clk[<N>] I Data from the GT
rx_serdes_data<4*N+3>[79:0] rx_alt_serdes_clk[<N>] I Data from the GT
fec_rx_din_start_<N> rx_alt_serdes_clk[<N>] I Indicates start of codeword.
fec_rx_din_start_<N>_bh rx_alt_serdes_clk[<N>] I Indicates start of codeword for bottom half of port. Used in 50G FEC-only mode.
rx_serdes_fifo_flagin_<N> rx_alt_serdes_clk[<N>] I Flag used to track timing through the RX slow-to-fast-clock FIFO; when asserted for a cycle, it will cause a corresponding assertion of _fifo_flagout after the FIFO retiming has occurred.
rx_serdes_fifo_flagout_<N> rx_serdes_clk[<N>] O Asserted after a fifo_flagin indication has progressed through the RX slow-to-fast-clock FIFO.
rx_serdes_albuf_restart_<N> rx_alt_serdes_clk[<N>] O Indicator that the alignment buffer needs to be reset for this port.
rx_serdes_albuf_slip_<4*N+0> rx_alt_serdes_clk[<N>] O Indicator that incoming data for this port needs to be delayed by one cycle.
rx_serdes_albuf_slip_<4*N+1> rx_alt_serdes_clk[<N>] O Indicator that incoming data for this port needs to be delayed by one cycle.
rx_serdes_albuf_slip_<4*N+2> rx_alt_serdes_clk[<N>] O Indicator that incoming data for this port needs to be delayed by one cycle.
rx_serdes_albuf_slip_<4*N+3> rx_alt_serdes_clk[<N>] O Indicator that incoming data for this port needs to be delayed by one cycle.