Timer Adjustment Mechanisms - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

To provide time-of-day timestamps on the local clock (either a RX SerDes recovered clock or TX SerDes clock), the PTP/System Timer running on the DCMAC Subsystem local clock needs to be synchronized to the master time-of-day timer running on the system timer clock ( ts_clk_N). The DCMAC Subsystem system timer can be synchronized with a master timer in a number of methods. Each port has independent internal free-running system_timer per RX and TX. For the following description, the D variable should be substituted with the desired TX and RX direction target and the N variable should be substituted by the target port number.