Time Representation - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The IEEE 1588 uses two types of time field formats:

Time-of-Day (ToD) Format
IEEE 1588-2008 format consisting of an unsigned 48-bit second field and a 32-bit nanosecond field. This format is compatible with version 1 of the standard.
Correction Field Format
Introduced in version 2 to handle Transparent clocks and better than 1 ns precision. It is a signed 64-bit integer in units of 2-16 ns. For example, 2.5 ns is represented as 64’h0000_0000_0002_8000.

The system_timer is implemented as an internal, unsigned linear counter which counts time in units of 2-40 ns. Each clock cycle system_timer is incremented by the quantity increment_value, which represents the period of the system timer clock in the same units. For example, for a nominal 644.0625 MHz clock, the increment value would be 42'h18D_3018_D302 (1,705,908,949,762 × 2-40 ns). This increment value is configured by the DCMAC Subsystem at start-up. If KP4-FEC is in use, a different initial value is configured: 42’h181_8181_8182.

The DCMAC Subsystem exposes 32 bits of the system_timer through the various timestamping interfaces (that is, TX and RX packet timestamps equivalent to a timer which counts in units of 2‑8 ns (that is, ~3.9 ps). User logic can map these 32 bits directly into Bits[39:8] of a correction field format timestamp. The upper bits of the system timer can be derived from the ptp_systemtimer input, because the values should be within the approximate latency of the RX or TX path. The bottom eight correction field bits should be set to 8’h0 as this degree of precision is not supported by the architecture. Note that this same mapping is used in 1-step timestamp insertion.

The least significant 32 bits (that is, < 2-8 ns portion of the counter) and the upper 23 bits of the DCMAC Subsystem system timer are not available through the timestamping interfaces. The lower bits allow the system_timer to be adjusted at fine-grained sub-nanosecond levels to track an external master clock as described in the next section.