TX Pause Generation - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English
A pause packet can be requested for transmission using the tx_pause_req_{0..5}[8:0] and c{0..5}_ctl_tx_pause_enable[8:0] input buses. Bit[8] corresponds to global pause packets and bits[7:0] correspond to priority pause packets. Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.--CAUTION! Requesting both global and priority pause packets at the same time results in unpredictable behavior and must be avoided.--The contents of the pause packet are determined using the per-port C{0..5}_CONFIGURATION_TX_FLOW_CONTROL_* registers which contain the following fields:
  • Global pause packets (N = 0..5):
    • cN_ctl_tx_da_gpp[47:0]
    • cN_ctl_tx_sa_gpp[47:0]
    • cN_ctl_tx_ethertype_gpp[15:0]
    • cN_ctl_tx_opcode_gpp[15:0]
    • cN_ctl_tx_pause_quanta8[15:0]
  • Priority pause packets (N = 0..5)
    • cN_ctl_tx_da_ppp[47:0]
    • cN_ctl_tx_sa_ppp[47:0]
    • cN_ctl_tx_ethertype_ppp[15:0]
    • cN_ctl_tx_opcode_ppp[15:0]
    • cN_ctl_tx_pause_quanta0[15:0]
    • cN_ctl_tx_pause_quanta1[15:0]
    • cN_ctl_tx_pause_quanta2[15:0]
    • cN_ctl_tx_pause_quanta3[15:0]
    • cN_ctl_tx_pause_quanta4[15:0]
    • cN_ctl_tx_pause_quanta5[15:0]
    • cN_ctl_tx_pause_quanta6[15:0]
    • cN_ctl_tx_pause_quanta7[15:0]
    The DCMAC Subsystem automatically calculates and adds the FCS to the packet. For priority pause packets, the DCMAC Subsystem also automatically generates the enable vector based on the priorities that are requested. To request a pause packet, you must set the desired bits of the c{0..5}_ctl_tx_pause_enable[8:0] bus to 1 at configuration time and then, at the desired point of transmission, set corresponding bits of tx_pause_req_{0..5}[8:0] bus to 1 and keep them at 1 for the duration of the pause request (that is, if these inputs are set to 0, all pending pause packets are canceled). The DCMAC Subsystem transmits the pause packet after the current packet in flight is completed – at the MAC core level; due to delays from the AXI interface an exact correlation between AXI-S packet relay and pause insertion cannot be guaranteed.
    Important: Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.
    To re-transmit pause packets, the DCMAC Subsystem maintains an independent timer per port. This timer is set according to the value of the corresponding register control. After a pause packet is transmitted for a given port, the per-port timer is loaded with the value of the c{0..5}_ctl_tx_pause_refresh_timer[8:0] field (in the C{0..5}_CONFIGURATION_TX_FLOW_CONTROL_TIMER register). When a timer times out, another packet for that priority (or global) is transmitted as soon as the current packet in flight is completed. Additionally, you can manually force a retransmission by setting the tx_resend_pause_{0..5} input to 1 for one clock cycle. Multiple concurrent pause frame transmission events are merged into single transmitted pause frames. 'Concurrent' in this sense means events that either happen on the same cycle (for example, multiple priority requests asserted (or de-asserted) at once) or that happen while waiting for the next pause frame insertion opportunity (end of packet currently in flight). Furthermore, new pause frame events (new tx_pause_req assertions) will override and reset the refresh countdown timer. For example, if the refresh timer is counting down with two active priorities and the user sends a request for a third priority, the two-priority refresh is forced to be timed out and a pause packet for all three priorities is sent as soon as the current in-flight packet (if any) is transmitted. You can stop pause packet generation by setting the appropriate bits of tx_pause_req_{0..5}[8:0] to 0.