System Clocks - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The abp3_clk signal is a mandatory clock which must be present and stable in all modes of operation. It is used for internal configuration and synchronization functions in addition to its use as a clock for the processor interface.