The DCMAC Subsystem reset structure consists of active-High reset signals for the core logic in each direction (TX and RX), the per-port PHY logic in each direction, and a common AXI4-Lite reset.
All resets are asynchronous inputs and are internally synchronized to the correct clock
domain for use. When asserted, resets must be held for a minimum of 24 ns or 8 × the cycle
time of the associated clock. For example, rx_core_reset must be held for 8 ×
rx_core_clk cycles.
Each part of DCMAC Subsystem has its own master reset
(rx_serdes_reset[5:0]/tx_serdes_reset[5:0] for PHY,
rx_core_reset/tx_core_reset for TSMAC). The pins should be
maintained in the reset state until all of the relevant clocks are stable.
In addition to pin-level resets, the DCMAC Subsystem can be software reset through the AXI4-Lite accessible reset registers.