Receive Pause Timer Handshaking Interface - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

A simple handshaking protocol is used to indicate the reception of pause packets and corresponding timer operation using the rx_pause_req[8:0] and rx_pause_ack[8:0] buses. For these buses, Bit[8] corresponds to global pause packets and Bits[7:0] correspond to priority pause packets. Both the _req and _ack buses have a corresponding _id (rx_pause_req_id[2:0], rx_pause_ack_id[2:0]) bus to indicate the port associated with the handshake.The following steps occur when a pause packet is received:

  1. If the corresponding bit of ctl_rx_pause_enable[8:0] is 0, the quanta is ignored and the DCMAC Subsystem’s Rx pause timer logic stays in step 1. Otherwise, the corresponding bit of the rx_pause_req[8:0] bus is set to 1, and the received quanta is loaded into a timer.If one of the bits of ctl_rx_pause_enable[8:0] is set to 0 (disabled) when the pause processing is in step 2 or later, the core completes the steps as normal until it comes back to step 1. Deasserting a bit of ctl_rx_pause_enable does not immediately cause the associated timer to expire.
  2. If c{0..5}_ctl_rx_check_ack (a register control field) is 1, the DCMAC Subsystem will wait for a rising edge on the appropriate bit of the rx_pause_ack[8:0] bus.If ctl_rx_check_ack is 0, the logic proceeds immediately to step 4.
  3. A rising edge on the correlated bit of rx_pause_ack[8:0] is received.
  4. The DCMAC Subsystem counts down the timer.
  5. When the timer expires, the DCMAC Subsystem sets the appropriate bit of rx_pause_req[8:0] back to 0, then returns to waiting for a pause packet to arrive.

If at any time during step 2 to step 5 a new pause packet is received, the timer is updated with the newly acquired quanta value and the process continues. The basic handshake process is shown below.

In cycle 3, pause frame receipt is indicated for port 0 with the assertion of rx_pause_req. (Although rx_pause_req and rx_pause_ack are 9-bit buses, they are shown here as single bit for clarity.) Connected user logic responds with an assertion of rx_pause_ack alongside rx_pause_ack_id of 0. That event is shown quickly in response to the request, but a normal system response would see those two events separated by whatever time is required for the system to halt transmission of data into the DCMAC Subsystem’s Tx path. Once the positive edge of rx_pause_ack is seen for port 0, the internal system timer for the received priority (or global) quanta will begin counting down. When the indicated quanta time (from the received frame) has elapsed, rx_pause_req will be de-asserted. The acknowledge in this case is de-asserted after the ack, but that need not be the case.