Receive MAC Interface - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The ingress ("network") side of the DCMAC Subsystem’s independent mode MAC receive path is a simple time-sliced 66b PCS block interface. There are four primary signals (all inputs):

  • rx_macif_ts_id[5:0] indicates the channel ID currently active on the interface.
  • rx_macif_ena indicates that the cycle is valid.
  • rx_macif_data<L> contains the PCS data recovered from the network, where <L> represents a data lane.
  • rx_macif_status is used to communicate the overall state of the receive link.

The rx_macif_data interface consists of 24 separate signals, each 66 bits (one PCS block) wide. The rx_macif_status signal should be asserted by the user logic to indicate a coherent/aligned 66b block stream. It should be deasserted when any of the following conditions exist:

  • PCS reports not_PCS_aligned
  • HI_BER
  • Test pattern generation