Protocol Support - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
Release Date
2.1 English
  • IEEE 1588 1-step and 2-step timestamping supporting both boundary clock and transparent clock
  • Custom preamble insertion, received preamble extraction
  • Programmable inter-packet gap (IPG)
  • Link status, alignment monitoring, and status reporting
  • 64B/66B decoding and encoding as defined in IEEE Standard for Ethernet (IEEE Std 802.3-2018)
  • Scrambling and descrambling using x58 + x39 + 1 polynomial
  • IPG insertion and deletion
  • Optional frame check sequence (FCS) calculation and addition in the transmit direction
  • FCS checking and optional FCS removal in the receive direction
  • Support for Clause 82 (100GE PCS) and Clause 119 (200GE, 400GE PCS) as well as per-channel control for processing based on Clause 49 PCS rules
  • Class-based and global flow control
  • Pause packet processing and transmission