Port Data Rate - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The DCMAC Subsystem architecture is composed of six independent Ethernet ports, each capable of a 100GE data rate. The port resources can be dynamically combined to produce higher (200GE and 400GE) IEEE Ethernet rates, up to an overall bandwidth of 600GE. The ports can be statically configured through the IP wizard or dynamically configured during run-time through the AXI4-Lite interface.

Note: Dynamically reconfiguring the port rates of the DCMAC Subsystem has clocking implications. Ensure that you understand the details surrounding clocking if you intend to take advantage of this capability.

The port data rates are configured using the following fields:

  • For TX, the c0_ctl_tx_data_rate, c2_ctl_tx_data_rate, and c4_ctl_tx_data_rate fields of the C0_TX_MODE_REG, C2_TX_MODE_REG, and C4_TX_MODE_REG registers.
  • For RX, the c0_ctl_rx_data_rate, c2_ctl_rx_data_rate, and c4_ctl_rx_data_rate fields of the C0_RX_MODE_REG, C2_RX_MODE_REG, C4_RX_MODE_REG registers.

Supported configurations are shown in the following table. N/A denotes that the data rate is not supported by that port.

Table 1. Port Data Rate
Port Configurable Modes ( c<N>_ctl_tx_data_rate / c<N>_ctl_rx_data_rate )
100GE 200GE 400GE
1 N/A N/A
2 N/A
3 N/A N/A
4 N/A
5 N/A N/A

Port 0 can be configured for operation at 100GE, 200GE, or 400GE data rates. However, while operating at 200GE data rate, port 0 consumes the datapath resources of port 1. When port 0 is configured for 400GE data rate operation, the datapath resources of port 1, 2, and 3 are all consumed.

Similarly, when port 2 is configured for 200GE data rate, it consumes the datapath of port 3, and when port 4 is configured for 200GE date rate, it consumes the datapath of port 5. Modes can be mixed and matched. For example, the user logic could configure ports 0 and 1 for 100GE data rate, port 2 for 200GE data rate, and ports 4 and 5 for 100GE data rate.

A change in the c<N>_ctl_tx_data_rate or c<N>_ctl_rx_data_rate register of any port requires that port to be reinitialized using the PHY reset and MAC flush after the configuration is complete.