Per-Port Statistics Monitoring - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
Release Date
2.1 English

The DCMAC Subsystem maintains internal statistics for each port including packet histogram statistics, as well as internal error statistics. The internal counters for the statistics are 47 bits wide (except for stat_rx_total_bytes, stat_tx_total_bytes, stat_rx_total_good_bytes, and stat_tx_total_good_bytes, that are 53 bits wide) and saturate when full.

A tick mechanism is used to snapshot the internal counter values and to place them in a set of accessible statistics registers. The values remain in the user-accessible registers until a subsequent tick overwrites the values with fresh data. The tick event also resets the internal counters to zero. In this method, the snapshot counter values represent a count of events which have occurred in the interval between tick events, making it easier to window the statistics. A tick event on a given port does not affect the statistics associated with any other port.

A tick event for the TX statistics is triggered by asserting a rising edge on the per-port tx_port_pm_tick[5:0] input pin for a given port, or by writing a 1 to the tick register of a given port through the AXI4-Lite interface. Similarly, a tick event for the RX statistics is triggered using the rx_port_pm_tick[5:0] input pin, or writing to the corresponding tick register.

Transferring data from the internal statistics engine to the user register space takes a number of clock cycles.

Completion of the update process for TX statistics is indicated by a single cycle assertion of the corresponding per-port AXI4-Lite tx_port_pm_rdy[5:0] pin. During the transfer, the port statistics counters are invalid and should not be read. Similarly, completion for the RX statistics is indicated by the corresponding rx_port_pm_rdy[5:0] pin.

When a snapshot is completed, the counter values are accessible on the 32-bit AXI4-Lite port, where the least significant 32 bits of the counter are stored at one address and the remaining most significant bits are stored at the next consecutive address.

In addition to the per-port internal statistics counters, the DCMAC Subsystem also outputs per-port statistics information onto the MAC statistics TDM interface, PCS statistics TDM interface, and RS-FEC statistics TDM interface. This allows user logic to maintain a set of counters, if desired.