Ingress Timestamping - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The ingress logic does not parse the ingress packets to search for 1588 (PTP) frames. Instead, it takes a timestamp for every received frame and outputs this value to the user logic. The feature is always enabled, but the timestamp output can be ignored if you do not require this function. The timestamp can be extracted from the rx_ptp_tstamp_out_<N> signal, where N is in the range of 0 to 5 and correlates to the port or to the SOP segment on the bus, depending on mode.

Timestamps are filtered after the PCS decoder to retain only those timestamps corresponding to a start of packet (SOP; the first data block after the SFD). In Coupled MAC+PCS modes, when AXI is selected as the output driver (using c{0..5}_ctl_pcs_rx_ts_en), the timestamp output bus is always correlated to the port number for rates below 400G; for example, port 2 will receive its timestamps on rx_ptp_tstamp_out_2. The 400G segmented AXI4-Stream bus has the possibility of two packet starts per cycle, and therefore uses two rx_ptp_tstamp_out buses. The rx_ptp_tstamp_out_0 bus is used for SOPs in segments 0–3 while rx_ptp_tstamp_out_2 is used for SOPs in segments 4–7.
Note: The upper most significant bits of the 55-bit timestamp are dropped due to output pin limitations. You can recreate them by using the rx_ptp_systemtimer input as reference accounting for roll-over as necessary (the delta between rx_ptp_tstamp_out and rx_ptp_systemtimer should be approximately the latency through the RX path, which is well within the span of time covered by the 32-bit value).
Note: rx_ptp_tstamp_out should be ignored for short packets.
Figure 1. Timestamp Ingress Interface