Flex Interface Timestamping - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

FLEX I/F 1588 timestamping is available when the DCMAC Subsystem is in the flex interface mode. Only 2-step timestamping is available and 1-step timestamping (insertion) is not supported. To enable the feature and associated ports, set the control bit c{0..5}_ctl_pcs_rx_ts_en to 1.

Note: Timestamping is not supported in FEC-only, FlexO, or 128GFC modes.

The RX FLEX I/F timestamps use the same output port as the normal ingress timestamps (rx_ptp_tstamp_out_<N>). Enabling FLEX I/F timestamps switches these ports over to the flexif clock. As decoding is not performed on the packet, the timestamp corresponds to the first word on the datapath and not the first word of the frame. For high accuracy, user logic can add block offsets to the timestamp value if the start of packet is not on the first word of the datapath.

In the egress direction, the FLEX I/F timestamping feature uses a different set of signals to request a timestamp and provide a tag (tx_ptp_flex_*_). However, the usual egress timestamp interface is used to produce the results.

Note: The egress timestamp output uses the tx_axi_clk regardless of the chosen timestamp mode. In cases where the AXI4-Stream interface is not being used, the tx_axi_clk frequency must still remain sufficiently high to support the maximum burst of PTP packets (the PTP packet rate is typically very slow).
Note: In addition to the tx_axi_clk, the tx_core_clk must also be running because the AXI reset logic is sequenced by the tx_core_clk domain. If the MAC and AXI4-Stream interface are not being used, the tx_core_clk can run at any rate (up to maximum supported) and can even be internally disabled using ctl_mem_disable_tx_core_clk.

An additional signal is present on the FLEX I/F in the egress direction: tx_ptp_flex_1588loc_in[2:0]/[1:0]. In the egress direction, the user logic is required to explicitly identify the lane containing the start of the packet (that is, the lane in which data following the start of frame delimiter (SFD) is present) indicating the block lane of the per-port signal. In this method, the TX timestamp accurately reflects the position of the start of packet.