Flex Interface Modes - 2.1 English - PG369

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-04-12
Version
2.1 English
The DCMAC Subsystem features a flex interface (FLEX I/F) which permits the user logic to bypass the MAC logic and directly access the internal hardened PHY resources of the DCMAC Subsystem. The FLEX I/F of each port can be configured to access a tap point within the internal DCMAC Subsystem transmit/receive PCS/FEC datapath. In this approach, the FLEX I/F of the port can be configured to expose any of the following tap points to the user logic:
  • Direct connection to the FEC resources
    • Option to bypass RX lane alignment
    • Option to bypass 256B/257B transcode
  • Scrambled 64B/66B blocks with alignment markers included
    • This supports a transparent mapping of 100GE into OTN.
  • Unscrambled 64B/66B blocks without alignment markers
    • This supports the mapping of 200GE, 400GE, and other rates into OTN.
    • This can also be used for Flex Ethernet (FlexE).
  • Unscrambled 64B/66B blocks with sync header error E-block replacement
    • This option only applies on the RX path.
    • This can be used when mapping to OTN or FlexE in some applications.
  • Unscrambled 64B/66B blocks with PCS state machine
    • This includes the state machine which results in the legalization of the 64B/66B block stream.

The FLEX I/F can be configured into between one and six independent ports, supporting 6 x 100GE, 3 x 200GE, and 1 x 400GE operation. Various combinations of these rates are also allowed. Furthermore, each 100G port can be bifurcated into two 50G interfaces when configured for FEC-only mode.

For each port, the operating data rate for the FLEX I/F is configured using the following fields:
  • For TX, the c0_ctl_tx_data_rate, c2_ctl_tx_data_rate, and c4_ctl_tx_data_rate fields of the C0_TX_MODE_REG, C2_TX_MODE_REG, and C4_TX_MODE_REG registers.
  • For RX, the c0_ctl_rx_data_rate, c2_ctl_rx_data_rate, and c4_ctl_rx_data_rate fields of the C0_RX_MODE_REG, C2_RX_MODE_REG, C4_RX_MODE_REG registers.

For the TX direction, the operating mode is set using the c0_ctl_tx_flexif_select through c5_ctl_tx_flexif_select of the C0_TX_MODE_REG through C5_TX_MODE_REG registers. For the RX direction, it is set using the c0_ctl_rx_flexif_select through c5_ctl_rx_flexif_select of the C0_RX_MODE_REG through C5_RX_MODE_REG registers.

You might wish to use a lower frequency clock for the FLEX I/F to ease timing closure in some device speed grades. To allow use of a reduced clock frequency, a special mode exists for port 0 to 3 that allows you to increase the width of a given 100G interface from 4 x 66-bit to 5 x 66-bit blocks. This mode is entered on transmit using the control fields c0_ctl_tx_flexif_pcs_wide_mode through c3_ctl_tx_flexif_pcs_wide_mode of the C0_TX_MODE_REG through C3_TX_MODE_REG registers. On receive, it is entered using the control fields c0_ctl_rx_flexif_pcs_wide_mode through c3_ctl_rx_flexif_pcs_wide_mode of the C0_RX_MODE_REG through C3_RX_MODE_REG registers.