Examples - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

The following shows timing diagram examples for the timer adjustments.

System Timer Overwrite

To overwrite the system timer, assert D_ptp_st_overwrite_N and drive the desired 54-bit value onto the input signal D_ptp_systemtimer_N. The overwrite is triggered by toggling the signal D_ptp_st_sync_N.

Figure 1. Timer Overwrite

As mentioned earlier, if the D_ptp_st_sync_N transition is sampled to the falling edge of the timer’s clock, a DDR phase compensator automatically adds half a clock period (that is, timer_increment / 2) to the system timer to help improve timer resolution.

Timer Frequency Set Coarse Adjustment

In this example, the system_timer frequency is set by providing a coarse adjustment to the timer_increment (Method 2 on the Adjustment Interface).

Figure 2. System Timer – Set Increment Value
Note: The 32-bit ptp_st_adjust value is interpreted as being in units of 2-8 ns, which means it is mapped into the coarse portion of the increment_value. The sub-nanosecond portion of the increment_value is set to 32’d0. To adjust the sub-nanosecond portion of the increment value, use the Timer Frequency Fine Adjust method.

Timer Frequency Fine Adjustment

Here is an example of fine-tuning the system_timer frequency by adjusting the sub-nanosecond portion of the increment value (Method 3 on the Adjustment Interface). The adjustment is specified to be in units of 2-40 ns. The provided signed adjustment value is added to the existing increment_value and used moving forward.

Figure 3. Fine Frequency Adjust

Phase Shift

In this diagram, a phase shift to the timer value is shown (Method 1 using the Adjustment Interface).

Figure 4. Phase Adjustment
Note: The increment_value only changes for one system_timer iteration (it is a one-shot adjustment) then returns to its previous value. The maximum allowable adjustment is a signed 18-bit value (two's complement) in units of 2-8 ns.