Enabling Receive Pause Timers - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
Release Date
2.1 English

Within the DCMAC Subsystem’s register space are per-port c{0..5}_ctl_rx_pause_enable controls that are 9 bits wide each. Setting any of those bits enables the DCMAC Subsystem’s corresponding internal pause timer. Enables 0 to 7 are used to activate the timer function for the corresponding priority while enable 8 is used to enable the global pause timer.