Figure 1. 1x400GAUI-8 GTM PAM4
Figure 2. 6x100GAUI-2 GTM PAM4
Figure 3. 3x200GAUI-4 GTM PAM4
For dynamic configuration, there are Phase FIFOs and CLK_MUXes placed between DCMAC and GT at the TX data path.
The Phase FIFO is an asynchronous XPM FIFO module with wr_clk and rd_clk. The rst of the FIFOs are connected with the gttxresetout from the GT Reset Controller IP within the dcmac core wrapper.
The wr_clk and rd_clk connections for the FIFOs are based on the dynamic switching configurations.