In addition to the AXI4-Lite configuration registers, the DCMAC Subsystem requires some control inputs illustrated in the following table. All control ports are inputs.
Note: In this table, <N> =
port number 0-5 and <V> is the VL lane number 0 to 19.
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| ctl_rsvd_in[119:0] | async | I | Reserved |
| ctl_vl_marker_id<V>[63:0] | async | I | Alternate AM definition. Activate with ctl_tx_use_custom_vl_marker_ids and/or ctl_rx_use_custom_vl_marker_ids as required. |
| c<N>_ctl_tx_pause_enable[8:0] | tx_axi_clk | I | TX Pause Packet Enable |
| c<N>_ctl_tx_send_idle_pin | tx_axi_clk | I | Transmit Idle Sequence ordered sets. If this input is sampled as a 1, the TX path only transmits Idle Sequence ordered sets. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) Sequence ordered sets. |
| c<N>_ctl_tx_send_lfi_pin | tx_axi_clk | I | Transmit Local Fault Indication (LFI) Sequence ordered set. Takes precedence over RFI. |
| c<N>_ctl_tx_send_rfi_pin | tx_axi_clk | I | Transmit Remote Fault Indication (RFI) Sequence ordered set. If this input is sampled as a 1, the TX path only transmits Remote Fault Sequence ordered sets. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner. |
| ctl_tx_custom_vl_length_minus1[15:0] | async | I | Defines the custom vl length (minus 1) to be used for any ports that have ctl_tx_use_custom_vl_length_minus1 == 1. The definition for the signal depends on the operating mode. For 100G, it is alignment length - 1 in 66b words per PCS lane (default value is 16383). For 200G and 400G, it is the number of FEC codewords (default value for 200G is 4096 and for 400G is 8192). |
| c<N>_ctl_tx_lane0_vlm_bip7_override | async | I | Indicates that the bip7 byte value is overridden. |
| c<N>_ctl_tx_lane0_vlm_bip7_override_value[7:0] | async | I | Indicates the override value for the bip7 byte. |
| tx_fec_am_sf_0[2:0] | tx_alt_serdes_clk[0] | I | For 200GE/400GE, these are the tx_am_sf degrade bits that are inserted into the AM. |
| tx_fec_am_sf_2[2:0] | tx_alt_serdes_clk[2] | I | For 200GE/400GE, these are the tx_am_sf degrade bits that are inserted into the AM. |
| tx_fec_am_sf_4[2:0] | tx_alt_serdes_clk[4] | I | For 200GE/400GE, these are the tx_am_sf degrade bits that are inserted into the AM. |
Note: Note: In the following table, <N> = port number 0-5.
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| ctl_rx_custom_vl_length_minus1[15:0] | async | I | Defines the custom VL length (minus) to be used for any ports that have ctl_rx_use_custom_vl_length_minus1 == 1. The definition for the signal depends on the operating mode. For 100G, it is alignment length - 1 in 66b words per PCS lane (default value is 16383). For 200G and 400G, it is the number of FEC codewords (default value for 200G is 4096 and for 400G is 8192). |
| c<N>_ctl_rx_pause_enable[8:0] | rx_axi_clk | I | RX Pause Packet Enable |