Clocking Relationships - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-04-12
Version
2.1 English

The DCMAC Subsystem assumes no phase alignment between any clocks. Any phase is tolerated, even between clocks that are synchronous (in frequency) to each other.

The following table shows the clock frequency relationships in Coupled MAC+PCS mode.

Table 1. Coupled MAC+PCS Mode - Clock Relationships
Mode AXI-S Width 1 Frequency of Rate Defining Clock (MHz) Frequency of Related Clocks (MHz) 2 Additional Frequency Relationships
100GE MAC+PCS with and without RS(528,514) FEC 256 tx_serdes_clk = 644.5313 +/- 100 ppm

rx_serdes_clk = 644.5313 +/- 100 ppm

tx_core_clk >= 781.25 + 100 ppm

rx_core_clk >= 781.25 + 100 ppm

tx_axi_clk >= 390.625 + 100 ppm

rx_axi_clk >= 390.625 + 100 ppm

tx_axi_clk >= tx_core_clk/2

rx_axi_clk >= rx_core_clk/2

100GE MAC+PCS with and without RS(528,514) FEC 512 tx_serdes_clk = 644.5313 +/- 100 ppm

rx_serdes_clk = 644.5313 +/- 100 ppm

tx_core_clk >= 390.625 + 100 ppm

rx_core_clk >= 390.625 + 100 ppm

tx_axi_clk >= 195.3125 + 100 ppm

rx_axi_clk >= 195.3125 + 100 ppm

tx_axi_clk >= tx_core_clk/2

rx_axi_clk >= rx_core_clk/2

100GE MAC+PCS with RS(544,514) FEC

200GE MAC+PCS

400GE MAC+PCS

256

tx_serdes_clk = 664.0625 +/- 100 ppm

rx_serdes_clk = 664.0625 +/- 100 ppm

tx_core_clk >= 781.25 + 100 ppm

rx_core_clk >= 781.25 + 100 ppm

tx_axi_clk >= 390.625 + 100 ppm

rx_axi_clk >= 390.625 + 100 ppm

tx_axi_clk >= tx_core_clk/2

rx_axi_clk >= rx_core_clk/2

100GE MAC+PCS with RS(544,514) FEC 512

tx_serdes_clk = 664.0625 +/- 100 ppm

rx_serdes_clk = 664.0625 +/- 100 ppm

tx_core_clk >= 390.625 + 100 ppm

rx_core_clk >= 390.625 + 100 ppm

tx_axi_clk >= 195.3125 + 100 ppm

rx_axi_clk >= 195.3125 + 100 ppm

tx_axi_clk >= tx_core_clk/2

rx_axi_clk >= rx_core_clk/2

  1. Bits per 100G.
  2. Clocks in this column represent the minimum required frequency. As such, the requirement is +100 ppm minimum (not +/-100 ppm). The clock source must be configured to ensure that even at the lower bound of its operational range (all uncertainties included), the minimum is achieved. These minimum frequencies are based on nominal clock frequencies for other related clocks. If other related clocks are scaled, then clock frequencies in this column must be likewise scaled.

The following table shows the clock frequency relationships for the standalone MAC when running in Independent MAC and PCS+FEC mode.

Table 2. Independent MAC and PCS+FEC Mode - MAC Clock Relationships
Mode Frequency of Rate Defining Clock (MHz) Frequency of Related Clocks (MHz) 1 Frequency Relationship to Rate Defining Clock
400G TX Channelized MAC tx_macif_clk = 260.4167

tx_axi_clk >= 260.4167

tx_core_clk >= 520.8333

tx_axi_clk >= tx_macif_clk

tx_core_clk >= 2 x tx_macif_clk

600G TX Channelized MAC tx_macif_clk = 390.625

tx_axi_clk >= 390.625

tx_core_clk >= 781.25

tx_axi_clk >= tx_macif_clk

tx_core_clk >= 2 x tx_macif_clk

400G RX Channelized MAC rx_macif_clk = 260.4167

rx_axi_clk >= 260.4167

rx_core_clk >= 520.8333

rx_axi_clk >= rx_macif_clk

rx_core_clk >= 2 x rx_macif_clk

600G RX Channelized MAC rx_macif_clk = 390.625

rx_axi_clk >= 390.625

rx_core_clk >= 781.25

rx_axi_clk >= rx_macif_clk

rx_core_clk >= 2 x rx_macif_clk

  1. Clocks in this column represent minimum required frequency. As such, the requirement is +100 ppm minimum (not +/-100 ppm). The clock source must be configured to ensure that even at the lower bound of its operational range (all uncertainties included), the minimum is achieved. These minimum frequencies are based on nominal clock frequencies for other related clocks. If other related clocks are scaled, then clock frequencies in this column must be likewise scaled.

The following table shows the clock frequency relationships for the standalone PHY logic when running in Independent MAC and PCS+FEC mode.

Table 3. Independent MAC and PCS+FEC Mode - PHY Clock Relationships
Mode FLEX I/F Width 1 Frequency of Rate Defining Clock (MHz) Frequency of Related Clocks (MHz) 2
100G PCS with and without RS(528,514) FEC 4x66 tx_serdes_clk = 644.5313 +/- 100 ppm

rx_serdes_clk = 644.5313 +/- 100 ppm

tx_flexif_clk >= 390.625 + 100 ppm

rx_flexif_clk >= 390.625 + 100 ppm

128GFC 3 4x66 tx_serdes_clk = 701.25 +/- 100 ppm

rx_serdes_clk = 701.25 +/- 100 ppm

tx_flexif_clk >= 425 + 100 ppm

rx_flexif_clk >= 425 + 100 ppm

100G PCS with RS(544,514) FEC

200G PCS

400G PCS

4x66 tx_serdes_clk = 664.0625 +/- 100 ppm

rx_serdes_clk = 664.0625 +/- 100 ppm

tx_flexif_clk >= 390.625 + 100 ppm

rx_flexif_clk >= 390.625 + 100 ppm

100G PCS with and without RS(528,514) FEC 5x66 tx_serdes_clk = 644.5313 +/- 100 ppm

rx_serdes_clk = 644.5313 +/- 100 ppm

tx_flexif_clk >= 322.27 4 + 100 ppm

rx_flexif_clk >= 322.271 + 100 ppm

100G PCS with RS(544,514) FEC 5x66 tx_serdes_clk = 664.0625 +/- 100 ppm

rx_serdes_clk = 664.0625 +/- 100 ppm

tx_flexif_clk >= 322.271 + 100 ppm

rx_flexif_clk >= 322.271 + 100 ppm

128GFC 3 5x66 tx_serdes_clk = 701.25 +/- 100 ppm

rx_serdes_clk = 701.25 +/- 100 ppm

tx_flexif_clk >= 340 + 100 ppm

rx_flexif_clk >= 340 + 100 ppm

100G FlexO

200G FlexO

400G FlexO

320 tx_serdes_clk = 698.81 +/- 100 ppm

rx_serdes_clk = 698.81 +/- 100 ppm

tx_flexif_clk >= 349.40 + 100 ppm

rx_flexif_clk >= 349.40 + 100 ppm

100G FEC-only RS(528,514) FEC

2 x 50G FEC-only RS(528,514) FEC

320 tx_serdes_clk = 644.5313 +/- 100 ppm

rx_serdes_clk = 644.5313 +/- 100 ppm

tx_flexif_clk >= 322.27 4 + 100 ppm

rx_flexif_clk >= 322.27 4 + 100 ppm

100G FEC-only RS(544,514) FEC

2 x 50G FEC-only RS(544,514) FEC

320 tx_serdes_clk = 664.0625 +/- 100 ppm

rx_serdes_clk = 664.0625 +/- 100 ppm

tx_flexif_clk >= 332.03125 + 100 ppm

rx_flexif_clk >= 332.03125 + 100 ppm

  1. Bits per 100G.
  2. Clocks in this column represent the minimum required frequency. As such, the requirement is +100 ppm minimum (not +/-100 ppm). +100ppm requirement is only if the flexif clk is not related to the serdes clk. The clock source must be configured to ensure that even at the lower bound of its operational range (all uncertainties included), the minimum is achieved. These minimum frequencies are based on nominal clock frequencies for other related clocks. If other related clocks are scaled, then clock frequencies in this column must be likewise scaled.
  3. For transceiver lane serial rate up to 56.42 Gbps.
  4. Although the required minimum is 312.5 MHz, the recommended minimum is 322.27 MHz.