Clocking - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

This section describes the clocking for the various supported DCMAC Subsystem configurations. The DCMAC Subsystem has a high degree of configurability and a large number of available modes. To achieve a successful implementation, care must be taken to satisfy the clocking requirements described further.

The DCMAC Subsystem features the ability to dynamically reconfigure ports to different data rates. For example, the DCMAC Subsystem could be dynamically reconfigured during run-time from a 6 × 100G configuration to a 1 x 400G configuration, while 2 x 100G remain unchanged. This type of reconfiguration has clocking implications. In 4 × 100G, each port can have independent tx_serdes_clk[5:0] sources. When the DCMAC is reconfigured into 1 x 400G mode, it is possible for the entire 400G to use tx_serdes_clk[0] without using tx_serdes_clk[3:1] clocks. If dynamic reconfiguration is not required, the relevant clocks can be statically connected to the DCMAC.