Channel Request - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

There are four channel request signals for transmit operation:

Indicates the DCMAC Subsystem is ready for ID requests.
Indicates a valid id request by the user logic.
The channel ID being requested.
SIC adjustment amount for the indicated channel.

The rdy signal is the only output from the DCMAC Subsystem and its purpose is to indicate that the MAC I/F is ready to accept new valid ID requests. The rdy signal is asserted when the core is out of reset and is deasserted whenever the channel/ID request pipeline between the MAC I/F and the channelized AXI I/F exceeds an internal non-programmable threshold.

The system designer is responsible for implementing MAC I/F user logic that feeds all downstream network/line ports at their specified rate. Correspondingly, it is expected that the DCMAC Subsystem core and AXI logic be provided with clocks that are fast enough to meet or exceed the bandwidth demands. The result is that the rdy signal should always be asserted after reset; the DCMAC Subsystem in such applications will not be the bandwidth bottleneck. If, however, the DCMAC Subsystem core clock is set at a frequency intended to provide rate limiting backpressure to the MAC I/F client (not recommended), the rdy signal could be used to indicate an overage of channel requests. The response of the client in such cases should be to halve the input request rate until rdy is reasserted or until further requests are not needed. The following diagram illustrates the operation of the MAC I/F.

Figure 1. Transmit MAC I/F Operation

The left side of the diagram (clock cycles 1 through 5) illustrates the expected behavior, with the MAC I/F user logic issuing channel requests after rdy is asserted, and moderating incoming data rate through deassertion of vld. This pattern is expected to continue indefinitely without the deassertion of rdy.

The supplemental idle count (sic) field is used for providing the MAC with network-side fine-tuning adjustment of its idle accumulation state. When a non-zero sic value is provided alongside vld, the indicated channel has its SIC accumulator adjusted by the indicated amount. With a six-bit value, adjustment can range from 0 (do nothing) to an adjustment of 63 (the maximum possible for each occurrence of the channel within the user logic calendar). The diagram illustrates non-zero sic adjustment requests in cycles labeled 5, 7, and 11.

The right side of the diagram (clock cycles 6 through 12) illustrates a point in time where the MAC I/F user logic has presented more channel requests back-to-back than the ID request pipeline in the DCMAC Subsystem can handle. The result is rdy deassertion, which must have a user logic response of lowering the incoming channel request (vld) rate to at least half. When rdy is once again asserted, the user logic can resume presenting vld requests at its desired rate.