Bus Operation Example - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

In the following figure a typical sequence of frame receipt is shown. Some details (for example, the err field) are not shown to keep the diagram compact. This figure depicts a channelized flow of frame data on port 0 through 5. Upper case is used for signal names in this diagram to differentiate between the channelized and non-channelized illustrations.

Figure 1. Channelized Segmented AXI4-Stream Typical Sequence of Frame Receipt

The details of this diagram are as follows:

  • Cycle #1 presents channel 0 information, starting with no data and ending with a complete frame on the upper part of the bus.
    • Segments 0–5 have their ena signals deasserted.
    • The sop is on segment 6; the eop on segment 11.
    • The received preamble associated with the segment 6 sop is presented on rx_preambleout_2. The rx_preambleout_0 is used for sop signals on segments 0–3, rx_preambleout_2 is used for sop signals on segments 4–7, and rx_preambleout_4 is used for sop signals on segments 8–11.
  • Channel 1 is active on cycle #2 and completes a previously started frame with an eop on segment 3.
  • Channel 2 data arrives on cycle #3, with three complete 64B frames.
    • The DCMAC Subsystem minimum receive frame size is 64B.
    • All three preamble buses are used to provide preamble information for sop signals in segments 0, 4, and 8.
    • eop signals occur on segments 3, 7, and 11.
      • All three corresponding mty indications would be zero (not shown).
  • Cycle #4 provides data for channel 3, starting with a 64B frame in segments 0–3, a two-segment gap, and then a new frame start in segment 6 that continues beyond this cycle.
  • Cycle #5 provides the end of a frame for channel 4 with eop in segment 9.
  • Cycle #6 shows a return of channel 2, with no data.
    • All ena signals are zero, which indicates that 12 segments of Ethernet idle were received from the data source for channel 2.
  • Channel 0 is presented for the second time in cycle #7; an 11-segment frame begins and ends, and then a new frame is begun on segment 11.
  • Cycle #8 shows tvalid deassertion; no channel information is provided.
    • Whenever the collective data sources do not require the AXI4bandwidth, idle cycles are seen on the RX AXI bus. If all rates and clocks are matched, this can still happen on start-up due to the asynchronous relay of data from the receive core to the AXI frontend.
  • More data is received for channel 3 in cycle #9, adding five more segments and terminating the frame that was begun in cycle #4.
  • Cycle #10 provides data for channel 5, ending a previously-started frame in segment 3, then starting and ending a new five-segment frame in segments 6–10.