2-Step Insertion - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

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2.1 English

Egress 2-step timestamping makes use of a timestamping command port which operates in conjunction with the AXI4-Stream data interface. The user logic requests a 2-step timestamp when the first cycle of data for the given frame is presented to the AXI4-Stream bus. Along with this request is a 8-bit timestamp tag, which is carried through to the egress timestamp interface.

After the timestamp is taken, the timestamp value (TS) is made available on the timestamp interface, along with the corresponding timestamp tag. The timestamp is a 55-bit value in the following figure.
Figure 1. Egress 2-Step Timestamp