Transceiver (SerDes) Interface - 2.1 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2023-07-11
Version
2.1 English

The clock and data connections between the MRMAC transceiver interface and the GT transceivers varies depending on the selected GT technology and the configured operating mode. This section describes the connectivity between the MRMAC and the GT Transceivers.

Table 1. Transceiver Interface Signal Descriptions
Port Name I/O Clock Description
rx_serdes_clk[3:0] I N/A Per-lane receive GT clock.
rx_alt_serdes_clk[3:0] I N/A Per-lane receive GT clock (x2 width mode).
tx_core_clk[3:0] I N/A Per-Port transmit GT clock. The same clock is used for all TX GT lanes for a given Port0-3. This clock is also used in the port core logic.
tx_alt_serdes_clk[3:0] I N/A Per-lane transmit GT clock (x2 width mode).
rx_serdes_reset[3:0] I rx_serdes_clk[3:0] Per-lane RX lane-logic reset.
tx_serdes_reset[3:0] I rx_serdes_clk[3:0] Per-lane RX lane-logic reset.
rx_serdes_data(0-3)[79:0] I rx_serdes_clk[3:0], rx_alt_serdes_clk[3:0] Receive GT data. This data is clocked by the associated rx_serdes_clk or the rx_alt_serdes_clk depending on operating mode.
tx_serdes_data(0-3)[79:0] O tx_core_clk[3:0],

tx_alt_serdes_clk[3:0]

Transmit GT data. This data is clocked by the associated tx_core_clk or the tx_alt_serdes_clk depending on operating mode.