Resets - 2.1 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2023-07-11
Version
2.1 English

The MRMAC reset structure consists of active-High reset signals for the SerDes, core logic of each port, and a common AXI4-Lite reset.

All resets are asynchronous inputs and are internally synchronized to the correct clock domain for use. When asserted, resets must be held for a minimum of 24 ns or 8 × the cycle time of the associated clock. For example, rx_core_reset[0] must be held for 8 × rx_core_clk[0] cycles.

The tx_core_reset and rx_core_reset are the master reset for the pins should be maintained in the reset state until all of the clocks to that port (rx_core_clk, tx_core_clk, rx_serdes_clk, rx_axi_clk, tx_axi_clk, rx_flexif_clk, tx_flexif_clk, tx_ts_clk, and rx_ts_clk) are stable.

In addition to pin-level resets, the MRMAC can be software reset through the AXI4-Lite accessible per-port reset registers.