Register Space - 2.1 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2023-07-11
Version
2.1 English

The MRMAC IP subsystem registers are accessible in a ZIP file on the AMD webpage. All registers are accessible through the AXI4-Lite interface.

When 1588 is enabled, an additional AXI4-Lite interface port appears on the MRMAC Wrapper, through which you can configure the Master timer. For more information contact Support.