In Low Latency mode, the AXI4-Stream interface is
clocked internally by the same high-speed clock connected to tx_core_clk and rx_core_clk pins (or
tx_core_clk and rx_serdes_clk pins when a port is
operating at 10/25GE data rate). By leveraging a single clock throughout the datapath, this
mode reduces latency by bypassing retiming stages and domain crossing buffering.
Even in the Low Latency mode, it is necessary to provide tx_axi_clk and rx_axi_clk clocks to enable
operation of certain high-performance device statistics and alarms, such as real-time FEC
alarms and flow control signaling.