In independent (asynchronous) clock mode, the AXI4-Stream interface is run off an independent clock which can be asynchronous to the other MRMAC clocks allowing maximum flexibility. For available AXI clocks, see Table 1.
Note: It is acceptable to provide the same clock to both transmit and receive
clock ports.
The port’s tx_axi_clk and rx_axi_clk clocks must be a frequency of at least 50% (or
greater) of the tx_core_clk and rx_core_clk (or rx_serdes_clk if the port is
operating in 10/25GE data rate). It is acceptable if the tx_axi_clk is driven by a source that is /2 of the tx_core_clk, and the rx_axi_clk is connected to
a source of /2 of the rx_core_clk (or /2 rx_serdes_clk if the port is operating in 10/25GE data rate).