1588 Control and Status Registers - 2.1 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID: PG314
Release Date: 2023-07-11
Version: 2.1 English

These registers are used to configure and fine-tune the Timestamping functionality.

Table 1. 1588 Control and Status Registers
CONFIGURATION_TX_1588 CONFIGURATION_RX_1588 Register Fields	Type	Description
ctl_ptp_st_offset[15:0]	RW	This is used to apply a fixed offset to ctl_ptp_st_systemtimer on an overwrite. The units of this bus are 2^-8 ns. Currently no default, but could be set to the equivalent of four clock cycles to match the latency due to metastability and pipeline flops.
sample_ptp_systimer[54:0]	RO	The current value of the system timer is captured on read (not using the ctl_ptp_sync).
sample_ptp_increment[41:0]	RO	The current value of the system timer increment value (in units of 2^-40 ns). This is for monitoring only. Adjustments are made using the PTP adjust interface.
ctl_tx_ptp_1step_enable	RW	This signal, when asserted enables 1-step operation.
ctl_tx_ptp_sat_enable[1:0]	RW	Saturation mode of the 1-step insertion logic. 2’b00: Wraparound (0x7FFFFFFF_FFFFFFFF → 0x80000000_00000000) 2’b01: Saturate to max positive 2’b10: Use Wrap/Saturate indications in incoming Correction Field Bits[1:0]. Note, in this mode, the eight LSB bits of the correction field are cleared. CF Bit[0]: Bit[62] of Ingress RX Timer Value (correction field format) CF Bit[1]: Sign of incoming correction/software generated field
ctl_tx_ptp_latency_adjust[19:0]	RW	This bus can be used to apply a fixed offset to the TX timestamp. The units of this bus are 2^-8 ns in 2's complement form.
ctl_rx_ptp_latency_adjust[19:0]	RW	This bus can be used to apply a fixed offset to the RX timestamp. The units of this bus are 2^-8 ns in 2s complement form.