Single Clock Mode - Single Clock Mode - 2.0 English - PG468

DRAM Semi-Ternary CAM 2.0 LogiCORE IP Product Guide (PG468)

Document_ID
PG468
Release_Date
2026-01-30
Version
2.0 English

Single clock mode is activated by specifying the same value for both LOOKUP_INTERFACE_FREQ and RAM_FREQ. The ram_clk port is not used in single clock mode. The Lookup interfaces, internal RAM and match logic are all clocked on the key_clk.

Note: Single clock mode is recommended for Lookup rates above 300 Mlps.