STCAM Bandwidth - STCAM Bandwidth - 2.0 English - PG468

Number of DRAM reads depends on the Lookup Rate as follows:

DRAM Reads = Lookup Rate × Average Number of Overlaps

A DRAM Read is either 64, 128 or 256 bytes depending on entry width calculated as follows:

ENTRY_WIDTH = KEY_WIDTH + RESPONSE_WIDTH + PRIORITY_WIDTH + RANGE_WIDTH + 11

Entry Width is rounded upwards to the closest DRAM Read size.

Lookup Read Bandwidth = DRAM Reads × (64, 128, or 256 bytes)

The Insert, Update, and Delete operations perform DRAM writes while the Lookup operation performs DRAM reads.

To maintain a consistent state in the CAM Database, the DRAM reads and writes must execute as described here. Write requests must execute only after all proceeding reads are complete. Also, all write requests must be acknowledged before subsequent read requests are performed.

Read completion and write acknowledgement introduce a 500 ns average latency. During this time, the DRAM is underutilized performing only a few write requests. The total lost time during one second can be calculated using the following equation:

DRAM Write Latency = 500E-9 × UPDATE_RATE

To compensate for the lost time, the DRAM bandwidth must be higher than the Lookup Read bandwidth to consume waiting DRAM read requests. The required DRAM BW is equal to the following value:

DRAM Bandwidth = 1/(1 - DRAM Write Latency) x Lookup Read Bandwidth

For example, if Lookup Rate = 30 Mlps, Entry Size = 64 B, Overlaps = 2, and Update Rate = 100 K operations per second, then the DRAM Read Bandwidth value is calculated as follows:

DRAM Read Bandwidth = 1/(1 - 500E-9 x 100E3) x 30E6 x 2 x 64 = 4.04 GB/s

In the above example, the DRAM Bandwidth became 5% higher than the Lookup Rate Bandwidth. To meet the required DRAM rate, the number of DRAM channels or HBM PCs should be selected in the following way:

RAW_PC_Bandwidth x PC_RANDOM_Bandwidth_UTIL_64B_RO x NUM_PCS >= DRAM_Bandwidth

Or

RAW_PC_Bandwidth x PC_RANDOM_Bandwidth_UTIL_128B_RO x NUM_PCS >= DRAM_Bandwidth

Or

RAW_PC_Bandwidth x PC_RANDOM_Bandwidth_UTIL_256B_RO x NUM_PCS >= DRAM_Bandwidth

The Raw Bandwidth is calculated by multiplying the width of the interface (excluding ECC pins) with the transfer rate of the interface. For example, DDR4-3200 operates at 3200 Mega-Transfers per Second (MT/s) per data pin on a 64-bit-wide interface, giving a raw bandwidth of 64 × 3200 Mb/s = 25.6 GB/s

The Read-Only Bandwidth utilization is different depending on the entry size. Wider entry provides better utilization.

• For HBM2E-3200, 40% for 64 B and 65% for 128 B.
• For DDR4-3200, 40% for 64 B and 78% for 128 B.

Dual channel LPDDR5 is supported. The width of the interface is 16 pins. Inline-ECC is used. LPDDR5-6400 using dual channel and inline-ECC has a utilization of 53% for 64 B.

One NMU per PC is sufficient except when the entry size is 128 B or wider, and a DDR4 or HBM memory is used.

The NMU must be clocked to sync with the RAM frequency. If a single NMU per PC/channel is used, RAM Frequency must not be below 350 MHz for HBM. For all other configurations, RAM Frequency must not be below 150 MHz.