The functional block diagram of the core is shown in the following figure.
Figure 1.
DRAM Semi-Ternary CAM Block Diagram
The DSTCAM core components are as follows:
- CAM Database
- Control registers and on-chip memory for algorithmic lookup matching.
- NoC master Units (NMUs)
- The table stored in DRAM, is accessed via the Network on Chip (NoC). CAM connects to the NoC using one or more NMUs.
- NMU FIFO
- A buffering queue for DRAM write and read requests. NMU FIFO ensures that all DRAM write requests from insert, update, or delete operations are completed before any lookup DRAM read requests are read from the FIFO.
- Lookup Request FIFO (Optional)
- Transfers Lookup Requests from the Lookup Frequency domain to the RAM Frequency domain.
- Lookup Response FIFO (Optional)
- Transfers Lookup Responses from the RAM Frequency domain to the Lookup Frequency domain.
- Management Request FIFO
- Buffering queue for input Management Requests.
- Management Response FIFO
- Buffering queue for Management Responses.
- Strict Priority Scheduler
- Schedules lookup and Management Requests.
- Shaper
- It ensures that the packet rate is not exceeded for a long period of time.
- AXI4-Lite interface slave
- Protocol handling for accepting read/write requests and generating responses. The AXI4-Lite interface uses 32 bits of data.
The following clock domains are depicted in previous DSTCAMblock diagram.
- AXI4-Stream Lookup Interface Frequency
- The clock frequency of the Lookup Request/Response interfaces. Depending on configuration parameters, a new Lookup Request can arrive at the end of every cycle, every second cycle, every fourth cycle, and so on.
- RAM Frequency
- The clock frequency of the internal RAM and match logic.
- AXI4-Lite Frequency
- The clock frequency of the AXI4-Lite bus.
The clocking of the CAM can be set to one of two modes:
- Single Clock Mode
- If the Lookup Interface Frequency and RAM Frequency are equal, then the RAM clock is not used, and the Lookup Request/Response FIFOs are removed completely.
- Dual Clock Mode
- If the RAM Frequency is higher than the Lookup Interface Frequency, shallow FIFOs are inserted to bridge the clock domains.