For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Note: When you generate the DSTCAM IP, Vivado also creates a SystemVerilog simulation package file named
<instance-name>_sim_pkg.sv. This package defines
a task named create that captures the configuration
settings for the DSTCAM IP instance. You
can import this package file and call its tasks in your own test bench, as
required.