Management Requests and AXI4-Lite - Management Requests and AXI4-Lite - 2.0 English - PG468

DRAM Semi-Ternary CAM 2.0 LogiCORE IP Product Guide (PG468)

Document_ID
PG468
Release_Date
2026-01-30
Version
2.0 English

Management Requests are of different widths.

The AXI4-Lite bus uses 32 bits of data. The API issues multiple 32-bit writes up to the width of the Management Request. The AXI4-Lite writes are assembled by the secondary AXI4 to a single Management Request. The AXI4-Lite interface is a standard type. Refer to AXI4-Lite IPIF LogiCORE IP Product Guide (PG155).

Note: AXI4-Lite imposes the following requirements when switching between read and write:
  • All outstanding write responses must have been received before issuing a read.
  • All outstanding read responses must have been received before issuing a write.