LPM Bandwidth - LPM Bandwidth - 2.0 English - PG468

DRAM Semi-Ternary CAM 2.0 LogiCORE IP Product Guide (PG468)
Document_ID
PG468
Release_Date
2026-01-30
Version
2.0 English

Number of DRAM reads depends on the Lookup Rate as follows:

DRAM Reads = Lookup Rate

A DRAM Read is 64 bytes.

Lookup Read Bandwidth = DRAM Reads × 64 bytes

The Insert, Update, and Delete operations perform DRAM writes while the Lookup operation performs DRAM reads.

To maintain a consistent state in the CAM Database, the DRAM reads and writes must execute as described here. Write requests must execute only after all proceeding reads are complete. Also, all write requests must be acknowledged before subsequent read requests are performed.

Read completion and write acknowledgement introduce a 500 ns average latency. During this time, the DRAM is underutilized performing only a few write requests. The total lost time during one second can be calculated using the following equation:

DRAM Write Latency = 500E-9 × UPDATE_RATE

To compensate for the lost time, the DRAM bandwidth is equal to the following value:

DRAM Bandwidth = 1/(1 - DRAM Write Latency) x Lookup Read Bandwidth

For example, if Lookup Rate = 30 Mlps, Entry Size = 64 B, and Update Rate = 100 K operations per second, then the DRAM Read Bandwidth value is calculated as follows:

DRAM Read Bandwidth = 1/(1 - 500E-9 x 100E3) x 30E6 x 64 = 2.02 GB/s

In the above example, the DRAM Bandwidth must be 5% higher than the Lookup Rate Bandwidth. To meet the required DRAM rate, the number of DRAM channels or HBM PCs should be selected in the following way:

RAW_PC_Bandwidth x PC_RANDOM_Bandwidth_UTIL_64B_RO x NUM_PCS >= DRAM_Bandwidth

The Raw Bandwidth is calculated by multiplying the width of the interface (excluding ECC pins) with the transfer rate of the interface. For example, DDR4-3200 operates at 3200 MT/s per data pin on a 64-bit-wide interface, giving a raw bandwidth of 64 × 3200 Mb/s = 25.6 GB/s

The Read-Only Bandwidth utilization is as 40% for both HBM2E-3200 and DDR4-3200.

Note: HBM and DDR4 use sideband ECC.

Dual channel LPDDR5 is supported. The width of the interface is 16 pins. Inline-ECC is used. LPDDR5-6400 using dual channel and inline-ECC has a utilization of 53%.

One NMU per PC is sufficient except.

The NMU must be clocked to sync with the RAM frequency. If a single NMU per PC/channel is used, RAM Frequency must not be below 350 MHz for HBM. For all other configurations, RAM Frequency must not be below 150 MHz.