|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC,
AMD Versal™ HBM Series |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream, AXI4-Memory
Mapped |
| Resources |
CDCAM Specification Tab
|
| Provided with
Core
|
| Design Files |
Encrypted Verilog RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraint (XDC) |
| Simulation Model |
Verilog source code |
| Supported S/W Driver
2
|
Standalone |
| Software Example Design Application |
Standalone, AMD Vivado™
IP integrator |
| Tested Design Flows
3
|
| Design Entry
4
|
Standalone, Vitis Networking P4, AMD Vivado™
IP integrator |
| Simulation
5
|
For the supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release
Notes and Known Issues |
Master Answer Record: N/A
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
-
Standalone
driver details can be found at the CAM IP webpage.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- CAM IP is supported only on Linux OS. Vivado IP catalog running on Windows does not support CAM IP.
- Siemens EDA ModelSim DE, Siemens EDA Questa Advanced Simulator,
Synopsys VCS, Cadence Xcelium Parallel Simulator, and AMD Vivado™
Simulator Xsim are supported, for more information on the compatible versions, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|