DRAM read and write requests are buffered in the NMU FIFO while they wait for a previous write request to finish its read completion and the write acknowledgement phases. The buffers are large enough to hold all requests without issuing flow control to the CAM Database. Flow control can be issued to the CAM Database only if the sum of reads divided by the sum of lookups during the write acknowledgment waiting time exceeds the average number of overlaps, and the DRAM operates at its bandwidth limits (that is, no extra DRAM bandwidth is available).
When the CAM Database receives flow control, it continues to operate. When its internal buffers become full, flow control is sent to the Strict Priority Scheduler. When the buffers of the Lookup Request FIFO and the Management Request FIFO get full, flow control propagates to the Lookup Request Interface and the AXI4-Lite Interface respectively.
If the Lookup Response FIFO is full, flow control is sent to the CAM Database.
Flow control is released only after congestion ends.