- Associative array containing arbitrary (key, mask, priority, response) entries.
- Ternary match key lookup returns hit/miss result and associated response value on hit.
- High throughput of up to 150 Million lookup per second (Mlps) using a single DRAM channel.
- Up to eight 32-bit wide range comparison fields in each rule minimizes the need for costly rule expansion.
- Flexible: Supports a wide range of key widths, response widths, and lookup rates with optimized resource utilization.
- Optimized Usage Option: Longest Prefix Matching (LPM) mode offers 128 prefix masks and key compression allowing efficient resource utilization and storage of IPv4, IPv6, and VPN routes.
- High Storage Efficiency: 90% of the DRAM bits are transformed into CAM bits.
- Supports all key widths up to 992 bits and all response widths up to 1024 bits.
- Supports tables with millions of entries using DRAM storage: HBM, DDR4, and LPDDR5.
- Supports up to 1024 unique masks.
- Supports up to four Pseudo Channels (PCs) for Versal devices using an HBM.
- Connects to memory controller over Network on Chip (NoC) using AXI4 Memory Mapped protocol.
- Supports entry insert, delete, and update using highly portable software APIs.
- Supports single channel for DDR4.
- Supports 16-bit dual-channel for LPDDR5.
- Supports entry insert, delete, and update using standard TCAM like software APIs. For LPM, a LPM style software API is used.
- Supports AMD Vivado™ IP integrator.