Entries are stored in DRAM. The DRAM ECC protection is handled by the
Memory Controller and is not described in this document. In addition to DRAM, some
on-chip Block RAM/Ultra RAM is also used. All on-chip memories in the CAM database are
ECC protected. There are eight additional ECC bits for every address in a 64-bit wide
memory. The eight additional bits are only used for ECC and cannot be used for storage.
64-bit wide memories are always referred to in this document (even though 72 bits are
used).
A scrubbing mechanism starts regularly (1 ms interval) and reads every
memory address of the CAM in the background using idle cycles. If a single-bit error is
detected during scrubbing, the error is corrected permanently by writing the corrected
data back to memory. Single-bit errors detected during lookup operations are corrected
dynamically. If a double-bit error is detected during lookup, there is no match. In
general, if double-bit errors are detected during lookup, it is recommended to drop the
packet issuing the lookup. There are two statistic counters for ECC:
Single-bit errors
This counter increments for single-bit errors detected and
corrected during scrubbing.
Double-bit errors
This counter increments for double-bit errors detected
during scrubbing.
The address of the first failing RAM location is stored in a register for
diagnostic purposes. There are two status outputs related to ECC: Single-bit/double-bit
error detected. The outputs are valid for one cycle (Lookup Interface clock domain)
whenever an error is detected by the ECC scrubber. The status outputs can be used to
trigger a CPU interrupt. When the CPU reads the statistics counters, the counters are
cleared.
The API provides a debug function to enable insertion of single-bit/double-bit
errors during write operations. With the error insertion enabled subsequent
insert/update/delete operations stores data in memory with errors.
Note: It takes up to 1 ms before the ECC
scrubber detects the errors which can be observed on the status outputs/error
counters.
The following ECC status is provided for lookup operations:
Single-bit errors
Not status per lookup operation, only indicated by ECC
scrubber.
Double-bit errors
Indicated in the lookup response status flag, together with
hit/miss indication.