Customizing and Generating the Core - Customizing and Generating the Core - 2.0 English - PG468

DRAM Semi-Ternary CAM 2.0 LogiCORE IP Product Guide (PG468)

Document_ID
PG468
Release_Date
2026-01-30
Version
2.0 English

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

The following are instructions on how to deploy the DRAM Semi-Ternary CAM using the standalone CDCAM IP.

DSTCAM IP version 2.0 (cdcam_v2_0) is released as part of the AMD Vivado™ Design Suite. The DSTCAM IP can be instantiated in Vivado in one of two different ways: using the IP integrator or using the IP catalog.