Constraining the Core - Constraining the Core - 2.0 English - PG468

Required Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections

AMD Versal™ design families are supported.

Clock Frequencies

The DSTCAM has three independent clocks:

key_clk

Used for the core logic and the interface to the NoC. The frequency is set using the parameter LOOKUP_FREQUENCY_INTERFACE and can range between 15 MHz and 400 MHz.

s_axi_aclk

For reading and writing key/response pairs to the CDBCAM over an AXI4-Lite interface. Up to 150 MHz.

mem_clk

Used for interface to the NoC. Up to 400 MHz (this value must be less than the key_clk frequency).

Clock Management

If CLOCKING_MODE = DUAL_CLOCK is selected, then the two clocks: LOOKUP_FREQUENCY_INTERFACE and RAM_FREQ must be sourced from the same clock generator (MMCM or PLL).

Clock Placement

This section is not applicable for this IP core.

Banking

For DDR IOBs, placement is dependent on the Versal device part number used. Refer to Configuring Memory IP in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).