Clocking - Clocking - 2.0 English - PG468

DRAM Semi-Ternary CAM 2.0 LogiCORE IP Product Guide (PG468)
Document_ID
PG468
Release_Date
2026-01-30
Version
2.0 English

All timing analysis has been performed on -2M speed grade. The DSTCAM clock domains are shown in the following table.

Table 1. DSTCAM Clocks
Clock Description
s_axi_aclk The AXI clock is used for table management. The AXI management interface has a completely asynchronous relationship with the lookup interface.
key_clk AXI4-Stream clock for Lookup Request/Response interfaces.
ram_clk The ram_clk is optional. It provides an option to clock the internal RAM and match logic on a separate high frequency clock. In most cases, this saves logic and memory resources.

Guideline:

  • key_clk <= 300 MHz, use ram_clk up to 600 MHz.
  • key_clk > 300 MHz, ram_clk is not used.